BSC Cross-Architecture HPC Benchmarks

The BSC Cross-Architecture HPC Benchmarks (SDV-CAB) are a curated suite of HPC kernels and algorithms — spanning dense linear algebra (BLAS Level 1–3), sparse solvers, FFT, stencils and memory / micro-benchmarks — implemented once and provided across multiple instruction-set architectures. Each kernel ships as a portable scalar reference plus hardware-tuned versions: hand-written vector intrinsics for RISC-V (RVV 0.7/1.0), x86 (AVX/AVX-512), Arm (NEON/SVE) and NEC SX-Aurora, GPU offload (CUDA/cuBLAS, OpenMP target), and optimised vendor-library back-ends (MKL, ArmPL). A common driver/kernel design isolates the architecture-specific code, so the same workload can be run and compared apples-to-apples across ISAs — turning RISC-V portability claims into reproducible numbers on performance, vectorisation efficiency and scalability. Released as open source (BSD 3-Clause) at https://gitlab.bsc.es/benchmarks/sdv-cab.

Compiler regression suites, architecture simulation, FPGA SoC validation, vector-unit tuning, university teaching labs

RISC-V CPU & accelerator startups; Established CPU/GPU vendors adding RISC-V IP; EuroHPC architecture & verification teams; Cloud-HPC providers evaluating heterogeneous nodes; Academic courses in computer architecture and parallel programming