Lagarto HUN

Lagarto Hun is a segmented scalar processor with in-order execution using the RISC-V open-source instruction set.

Institution:

Research Group:

Researcher/s:

Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J,Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, Victor Jiménez, Leonidas Kosmidis, Vatistas Kostalampros, Rubén Langarita, Guillem López-Paradis, Joan Marimon, Jonnatan Mendoza, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Carlos Rojas, Abraham Ruiz, Nehir Sonmez, Victor Soria, Osman Unsal, Mateo Valero, Iván Vargas

Website:

https://meep-project.eu/media/news/scalar-core-lagarto-hun-improvements

Description:

Lagarto Hun is a segmented scalar processor with in-order execution using the RISC-V open-source instruction set.

In collaboration between BSC and CIC-IPN, originally Lagarto Hun was a RV64IMA core with a 5-stage pipeline in order, supporting privileged ISA v1.11. As a first improvement, we have added support for single and double precision floating point operations, becoming Lagarto Hun into a RV64GCV + (subset RVV0.7.1) core, commonly named as RV64G for general purpose core.

Problem:

N/A

Solution:

N/A

Aplication areas:

N/A

Novelty:

N/A

Protection:

Solderpad Hardware License

Target market:

N/A

Keywords:

core, risc-v

TRL: N/A

CRL: N/A

BRL: N/A

IPRL: N/A

TmRL: N/A

FRL: N/A

More information

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